1. Field of the Invention
The present invention relates to a memory circuit used for data storage, and more specifically to a memory circuit in which the stored data can be read even when a source voltage decreases.
2. Description of the Related Art
The layout of a main portion of a typical memory circuit is shown in the circuit diagram of FIG. 5. In FIG. 5, an inverter 1 is connected to the gate of a transistor 3 via a switching transistor 2. A memory cell 4 for storing one bit of data is inserted between a power source (not shown) and the ground. The memory cell 4 is comprised of a selective (or selecting) transistor 5 and a memory transistor 6 which are serially connected to each other.
The selective transistor 5 is turned on by applying the gate voltage to the gate (the selective gate) when a word line WL is selected, and is applied with VBL as a bias voltage. A threshold voltage with which the selective transistor 5 is operated is set to 1.5V, for example. The memory transistor 6 is operable to store binary data (xe2x80x9c1xe2x80x9d/xe2x80x9c0xe2x80x9d) data according to the presence/absence of charged electric charge, the drain of which is connected to a bit line BL.
In this structure, the memory transistor is electrically charged when xe2x80x9c0xe2x80x9d data is written to the memory cell 4. In this case, when the word line WL is selected, a voltage is applied to the gate of the selective transistor 5 to turn on the selective transistor 5. The memory transistor 6 is then turned on due to the electric charge, thus making a current flow to the bit line BL, and the current is detected to read the xe2x80x9c0xe2x80x9d data.
On the other hand, if xe2x80x9c1xe2x80x9d data is written to the memory cell 4, the memory transistor 6 is not charged with electric charge. When the word line WL is selected, a voltage is applied to the gate of the selective transistor 5 to turn on the selective transistor 5. However, no existence of electric charge in the memory transistor 6 does not bring a current flowing to the bit line BL. In this state where there is no flowing current, the xe2x80x9c1xe2x80x9d data is read out.
In conventional memory circuits, as a source voltage VCC decreases when the data is read, the gate voltage applied to the gate of the selective transistor 5 decreases accordingly. This results in difficulty in flowing the drain current because a difference between the threshold voltage of the selective transistor 5 and the gate voltage of the selective transistor 5 becomes smaller as the source voltage VCC is dropped to, for example, 1.8 V or less.
Hence, in conventional memory circuits, the selective transistor 5 may not be turned on in a normal manner as the source voltage VCC decreases, causing a problem in which the charging state of electric charges in the memory transistor 6 cannot be confirmed and thus data cannot be read from the memory cell 4.
The present invention has been made from this context, and has an object to provide a memory circuit in which data can be read in a normal manner even when a source voltage decreases.
In order to attain the above object, the present invention provides a memory circuit having a memory cell provided at a cross point of a word line and a bit line, the memory cell comprising a selective transistor turned on when the word line is selected, and a memory transistor connected to the selective transistor for storing xe2x80x9c1xe2x80x9d/xe2x80x9c0xe2x80x9d data according to the presence/absence of electric charge, the memory circuit comprising: source voltage detection means for detecting a source voltage; booster means responsive to the detection result of the source voltage detection means to boost the source voltage to apply the boosted voltage to the word line if the source voltage becomes equal to or less than the threshold value of the selective transistor when the xe2x80x9c1xe2x80x9d/xe2x80x9c0xe2x80x9d data is read.
The source voltage is detected by the source voltage detection means when the xe2x80x9c1xe2x80x9d/xe2x80x9c0xe2x80x9d data stored in the memory transistor is read. When the source voltage becomes equal to or less than the threshold value of the selective transistor, the booster means boosts the source voltage to apply the boosted voltage to the word line. Therefore, since the gate voltage of the selective transistor is sufficiently high relative to the threshold value of the selective transistor when the word line is selected, the selective transistor may not be influenced from a drop of the source voltage and is turned on in a normal manner to read the xe2x80x9c1xe2x80x9d/xe2x80x9c0xe2x80x9d data from the memory transistor.
Further, according to the present invention, the above-described booster means boosts the source voltage so that this boosted voltage takes a value ranging from two or more times greater than the threshold voltage of the selective transistor up to the maximum value of the source voltage. In other words, the boosted voltage is controlled to be within a range between two or more times greater than the threshold voltage of the selective transistor and the maximum value or less of the source voltage. This allows the xe2x80x9c1xe2x80x9d/xe2x80x9c0xe2x80x9d data to be read from the memory transistor without any influence from a drop of the source voltage. Furthermore, the influence of the stress affected to the gate of the selective transistor by the boosted voltage can be equalized with that in the normal operation of the source voltage.
Still further, the memory circuit according to the present invention comprises boosted voltage detection means for detecting the boosted voltage, wherein the booster means is responsive to the detection results of the boosted voltage detection means to perform the boosting operation so that the boosted voltage is within the above range.
The memory circuit according to the present invention comprises the above-described boosted voltage detection means, employing an intermittent driving control in which the boosting operation is performed by the booster means if the boosted voltage is less than the lower limit of the above range while the boosting operation is stopped if the boosted voltage is over the upper limit of the above range. This prevents any excess boosting operation, thereby reducing the power consumption.
Still further, according to the present invention, the above-described booster means causes a high voltage when the data is written to the memory cell.
The booster means causes a high voltage when the data is written to the memory cell and causes the boosted voltage for the purpose of compensating for a drop of the source voltage during a read operation. The memory circuit according to the present invention employs the features of the conventional write booster means, thus making it possible to achieve relatively easy circuit structure.